Intel 8086 microprocessor architecture with memory, interrupts, I/O ports, registers, instruction set and addressing modes

Memory of 8086 microprocessor

All stacks, program and data occupy similar memory space and the total memory available for holding addresses is just 1MB. The addresses used by processors are mostly of 16 bit which thereby allows only 1024kb/16=64kb of address pointers to be handled effectively. If there is a need to access memory outside this 1MB allotted memory then the CPU uses special segment registers to specify the location of the code, stack and data 64 KB segments in the 1MB of memory. (refer the “Register” section below) 16-bit pointers and data are stored as: address: low-order byte address+1: high-order byte 32-bit addresses are stored in "segment:offset" format as: address: low-order byte of segment address+1: high-order byte of segment address+2: low-order byte of offset address+3: high-order byte of offset Physical memory address pointed by segment: offset pair is calculated as: address = ( * 16) +  



Program memory - The program can be located anywhere in the 1MB memory. To place a program within a short distance from the previous program within the 64 kb code segment or long distance within the 1MB of the memory one can use jump and call instructions. All jump commands can be used to place a program within the +127 - -127bytes from the current instruction. 

Data memory - The 8086 microprocessor can access the data from any of the 4 segments which means that in total there is 256 KB of accessible data for the microprocessor (in case when all the four 64 KB segment blocks point to different segments). To access any of the Data, Code, Stack or Extra segments one needs to use prefixes with the instructions, these prefixes are DS:, CS:, SS: or ES: (some registers and instructions use ES or SS segment rather than the DS segment by default) Word data can be located at even or odd or even byte boundaries although during usage of this memory value by microprocessor if the value is at even boundary then two memory accesses are required for the 16 bit memory value and for odd boundary value only one access is required.  

Stack memory - This can be place anywhere in the memory and is free to have odd memory address locations although it is not recommended for performance reasons (see “Data Memory” above)  

Reserved locations -

• 0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer in format segment:offset.
• FFFF0h - FFFFFh - after RESET the processor always starts program execution at the FFFF0h address.

Interrupts in 8086 microprocessor

8080 microprocessor can handle up to 256 software and hardware interrupts 8086 processor has two hardware interrupts: NMI – Non maskable interrupt. This means that it cannot be disable by user and is for emergency situations. Interrupt type of NMI is 2 which mean that the address of NMI processing routine is stored at 0008h. NMI has higher priority that the maskable interrupt. INTR – this is a maskable hardware interrupt. INTR interrupts can be enabled / disabled by the STI/CLI instructions or the more complicated system of updating the flag register. The flags are updated with the help of POPF instruction. After an interrupt is received from an external device, two acknowledging signals are issued through INTA signals. The first signal is issued to ask the external device to get ready and the second is issues soon afterwards. The interrupt signal is sent by the external device to the lower order data lines of 8086 microprocessor. The interrupt signal is in the form of an 8 bit number which is multiplied by four to get the starting address from the interrupt pointer table. During the T2 of the first acknowledge cycle to second acknowledge the LOCK signal remains in low and therefore any HOLD request is not honoured until the second bus cycle ends.  

Software interrupts in 8086 microprocessor

• INT instruction – This is a point 3 breakpoint interrupt
• INT instruction – Any one interrupt available out of the 256 interrupts.
• INTO instruction – Interrupt an overflow
Single-step interrupt – This is a type 1 interrupt and is generated when the TF flag is set. When the CPU processes this interrupt it clears the TF flag and then carries out the interrupt processing routine.
• Processor exceptions: divide error (type 0), unused opcode (type 6) and escape opcode (type 7).

I/O ports in 8086 microprocessor

These ports can be addressed as either 65536 8-bit I/O ports or 32768 16-bit I/O ports.

Registers in 8086 microprocessor

Most of the registers in the 8086 microprocessor contain the data/ instruction offsets within the 64 kb memory segments. In the 1MB of memory in the 8086 there are 4 different 64 kb memory segments viz., instructions, stack, data and extra data for which 8086 uses 4 different segment registers:

Code Segment: is a 16-bit register used to store the address of the 64 kb segment containing processor instructions. Any instruction referred by the instruction pointer register is accessed by the processor using the address in the Code segment. If there is a far call, far jump or a far return instruction by the processor such an address is automatically updated in the CS register.  
Stack Segment: is a 16-bit register used to store address of the 64 kb segment containing program stack. By default, 8086 assumes that any data reference by the stack pointer and base pointer register is located in the Stack Segment. SS segment can easily be changed by directly using the POP instruction.  
Data segment: is a 16-bit register used to store address of the 64 kb segment containing program data. By default, 8086 processor uses that data segment contains all the data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI). It can changed directly using the POP and LDE instructions.  
Extra Segment: is a 16-bit register used to store the address of the 64 kb along with the program data. 8086 microprocessor by default assumes that any instruction for string manipulation referred by DI register is referenced to the ES segment. ES segment can be changed directly using POP and LES instruction.

User can change the default segment used by the general and index register by prefixing the instruction with a CS, SS, DS or ES prefix.

All general registers can be used for any arithmetic or logical operations. The general registers are:  

Accumulator: is used for string manipulation and input output operations. It has 2 8-bit registers AL and AH which can be used together to function as a 16-bit register AX. When used as a 16-bit register, the AL register is used to store the lower order byte of the word and the AH register to store the higher order byte of the word.  
Base: contains 2 8-bit registers BL and BH, like in an accumulator, the registers are BL and BH and during the combination use as 16-bit register they are called BX. BL contain the lower order byte of the word and BH contains the higher order byte of the word. BX register usually contains a data pointer used for based, based indexed or register indirect addressing. BX as a special purpose register serves as a base for the computation of memory address.  
Count: contains 2 8-bit registers CL and CH which can be combined together and used as a 16-bit register CX. When combined, CL register contains the low-order byte of the word, and CH contains the high-order byte. Count register can be used as a counter in string manipulation and shift/rotate instructions. It can be used in case of multi-iteration instructions. When the content of CX registers become zero the process is terminated.  
Data: register consists of 2 8-bit registers DL and DH, which can be combined together and used as a 16-bit register DX. When combined, DL register contains the low-order byte of the word, and DH contains the high-order byte. DX registers are used during data transfer between the input/output port and the memory using certain input/output instructions to store memory addresses.