VHDL program coding for 1 bit comparator waveform Xilinx

A 1 bit comparator is a logic circuit made up of  AND, OR and NOT circuit and is used to compare 3 input conditions based on the 2 input and give an output correspondingly. The output arrives under 3 conditions which are:

A is greater than B (A>B)

A is equal to B (A=B)

A is less than B (A<B)

VHDL code to generate a 1 bit comparator with behavioral model

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity com1bit is

port(

A : in std_logic;

B : in std_logic;

Y0 : out std_logic;

Y1 : out std_logic;

Y2 : out std_logic

);

end com1bit;

architecture behavioral of com1bit is

begin

process(A,B)

begin

                if(A>B)

                                then Y0<='1';Y1<='0';Y2<='0';

                elsif (A<B)

                                then Y0<='0';Y1<='0';Y2<='1';

                else

                                Y0<='0';Y1<='1';Y2<='0';

                end if;

                end process;

end behavioral;

Level 1 Xilinx output for 1 bit comparator

Level 2 Xilinx output for 1 bit comparator

 

Logic gate circuit diagram for 1 bit comparator

 Truth table for 1 bit comparator

Inputs		Outputs
A	B	(Y0)A > B	(Y1)A = B	(Y2)A < B
0	0	0	1	0
0	1	1	0	0
1	0	0	0	1
1	1	0	1	0